ASIC Engineer, Implementation (University Grad)
Meta is seeking an ASIC Engineer to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design implementation of advanced IPs using state-of-the-art tools. Come work and learn alongside our expert ASIC engineers to build “Green” data center accelerators.
ASIC Engineer, Implementation (University Grad) Responsibilities
- Drive logic/physical synthesis and generate optimized Gate level Netlist for Physical Design.
- Analyze designs and enhance PPA (Power, Performance, Area).
- Develop Timing Constraints in SDC/Tcl for Synthesis/Static Timing Analysis.
- Perform LEC Checks between RTL and Netlist and debug the aborts/failing points.
- Implement ECO (Functional, timing) for fixing Netlist Issues.
- Perform RTL Lint, DFT, Clock Domain Crossing, Reset Domain Crossing checks.
- Support and develop Implementation Infrastructure, analyze and improve tool flows & methodology.
Minimum Qualifications
- Knowledge of Python, Perl or Tcl.
- Knowledge of CMOS Technology, Logic Gates, Flip Flops or similar.
- Knowledge of Computer Architecture, Digital Design or VLSI Design.
- Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
- Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
Preferred Qualifications
- Currently has, or is in the process of obtaining, a Masters degree in Electrical Engineering, Computer Engineering or related engineering fields.
- Knowledge of Verilog, VHDL or similar hardware description language.
- Creativity and problem solving capabilities.
- Experience with Logic Synthesis.
- Understanding of Timing constraints, Floor planning and Static Timing Analysis.
- Understanding of SRAM Memories.